1. Technical Field
Embodiments of the present disclosure generally relate an integrated circuit, and more particularly to semiconductor device having an input/output (I/O) line drive circuit that performs an active operation during a refresh operation in accordance with a command/address signal and semiconductor systems including the semiconductor devices.
2. Related Art
A semiconductor memory device may include word lines, bit lines, and memory cells coupled the word lines and the bit lines. When the semiconductor memory device stores data in the memory cells and outputs the data stored in the memory cells, the word lines and the bit lines are used. That is, the semiconductor memory device may receive a command and an address to execute an active operation, which includes a write operation for storing data in the memory cells and a read operation for outputting the data. In a case of a dynamic random access memory (DRAM), each memory cell may include a single cell transistor and a single cell capacitor, and data may be stored in the cell capacitors of the memory cells. The word lines may be connected to gates of the cell transistors to control switching operations of the cell transistors.
In the active operation, one of the word lines is selected to receive the data or to output the data.
When one of the word lines is selected to receive or output the data, the selected word line may be driven with a high voltage. The cell transistors connected to the selected word line may be turned on by the high voltage applied to the gates of the cell transistors, and as a result, a charge sharing occurs between the cell capacitors and the bit lines connected to the selected word line through the turned-on cell transistors.
The recent developments of mobile devices are leading to advances in technologies for low-power DRAM devices. The technologies for low-power DRAM devices may include the current reduction during refresh operations.
Unlike static random access memory (SRAM) devices or flash memory devices, the DRAM devices may lose data stored in their memory cells as time elapses. In order to retain the data stored in the memory cells, the DRAM devices perform a refresh operation by periodically reading data stored in a memory cell and immediately rewriting the read data to the same memory cell. The amount of time that the memory cells can safely retain data without being refreshed is called a retention time. Usually, a refresh operation is carried out at least once in a retention time.